1. Field of the Invention
The present invention relates to a digital signal processor (hereafter referred to as the DSP) including a logical operation circuit, a product-sum circuit, and registers.
The present application is based on Japanese Patent Application No. 2000-066536, which is incorporated herein by reference.
2. Description of the Related Art
The DSP includes a logical operation circuit, a product-sum circuit, and registers, adopts the so-called harbored architecture and a structure capable of program control for repetitive operation processing, and is widely used as it is optimal in continuous product-sum operation processing by an FIR filter (i.e., finite impulse response filter) or the like.
FIG. 1 shows a typical example of a related DSP. The DSP is comprised of a product-sum circuit (including pipeline registers, a multiplier, a bit expander, adders, and a limiter) including pipeline registers and adders for effecting pipeline processing of data, a logical operation circuit (including a logic), and registers (registers and product-sum memories MACH and MACL), and data memories (data memories X and Y) and an instruction memory are connected thereto.
For example, as shown in FIG. 2, a host computer 1 sets data necessary for operations in the aforementioned data memories (data memories X and Y) 4a and 4b through a PCI bus interface 2 and a local bus interface 3, causes a DSP 6 to perform operations, and obtains their results through the memories 4a and 4b. 
A program necessary for DSP operations is set in an instruction memory 5. The DSP 6 advances the program step of the instruction memory by a program counter in the internal registers.
However, in control using the above-described DSP, the host computer 1 basically merely inputs data necessary for operations to the DSP and sends control signals for starting or stopping the operation, while the DSP merely delivers the results of operation by handshaking with respect to those signals, and the DSP itself is merely designed to specifications for performing stand-alone operations. Accordingly, the host computer, when performing the DSP operation, is able to obtain only the results of operation by the DSP operation, and is unable to execute detailed processing routines which are not predetermined routine operations, so that there has been a drawback in that the scope of application is limited.
In addition, since it is impossible to directly access the internal registers, it has been necessary to separately provide a test circuit for the registers inside the DSP.